1. Field of the Invention
The present invention relates to the matching of digital patterns using analog logic.
2. Description of the Prior Art
Matching of digital patterns is often accomplished using digital logic, wherein an input pattern is matched against a reference pattern. For example, referring to FIG. 1, a general overview of one method shows a series of XOR gates 101 . . . 104 that have a first set of inputs A.sub.1. . . A.sub.4 and a second set of inputs B.sub.1 . . . B.sub.4, respectively. More generally, there may be n pairs of inputs to n XOR gates, where n is an integer. The binary digits of the input pattern are applied to the first set of inputs, and the binary digits of the reference pattern are applied to the second set of inputs, in order to perform "pair matches". When a pair match occurs, the A.sub.n input equals the B.sub.n input to a given XOR gate, and the given XOR gate output sets the associated control line (105, 106, 107 or 108) in a low state. However, when a pair mismatch occurs (i.e., when A.sub.n .noteq.B.sub.n), then the control line from the associated XOR gate output goes high. The number of pair mismatches may then be counted in a series of counters comprising first stages (109 and 110) and one or more subsequent stages (111), depending on the number of values to be matched. The output of the counter 118 represents the total number of pair mismatches, which is supplied via bus 112 to a comparator 113. A number of allowed pair mismatches, for example 2 mismatches, is supplied to the comparator via bus 114. If the number of pair mismatches on bus 112 is less than or equal to the allowed number on line 114, then the comparator provides a "pattern match" signal on comparator output line 115. Otherwise, a "pattern mismatch" signal is supplied on line 115.
As the number of values to be matched increases, the complexity of the counter 118 increases. This means that not only more first stage counters must be provided, but also more subsequent-stage counters. Hence, both the circuit complexity and size increases, and also the delay through the counter increases as the number of inputs (n) increases. Other pattern-matching techniques include the use of software programs, but they are typically not as fast as hardware-implemented techniques.